1. Field of the Invention
The present invention generally relates to the fabrication of electronic circuit devices and, more particularly, to the in-situ formation of solder deposits especially of a size appropriate to solder connections between carriers or substrates and chips or other substrates or carriers where a significant gap may exist.
2. Description of the Prior Art
Formation of electrical and mechanical connections between elements of an electronic device has long been known, particularly for attachment of discrete components and integrated circuits to carriers such as printed circuit boards. As component sizes have been reduced and in the course of production runs of particular electronics devices and portions thereof, many sophisticated techniques for forming such connections by soldering have been developed, particularly for forming numerous connections concurrently and at close spacing.
In particular, in modular circuit packaging, in which numerous connections are formed in layers on lamina which are later stacked and sintered or otherwise fused to provide a complex interconnection structure for the interconnection of numerous integrated circuit chips which may be mounted thereon, soldering techniques have been developed by which the chips can be mechanically mounted and also form potentially thousands of connections to each chip in a very closely spaced array. For this purpose, the technique of application of solder materials and flux has become quite critical, particularly as to volume of solder materials. If too much solder is used, the solder material may form unwanted bridges between closely spaced conductors and/or connection pads. If too little solder is used, the mechanical and/or electrical integrity of the connection may be severely compromised, if a solder connection can be formed at all.
Generally the amount of solder required for a particular connection depends on the area of the connection and the physical proximity of the surfaces which are to be connected. Solder can successfully bridge relatively small gaps and, by adjustment of solder-wettability of surface surrounding the connection, solder flow can generally be well-controlled within the boundaries of the surfaces to be connected and which must necessarily be solder wettable. However, the volume of solder, if too great for a given area and surface separation, may be sufficient to cause solder flow across surfaces which are not solder wettable. Conversely, if the separation of surfaces is too great to be bridged by the volume of solder available, the solder will merely form bumps on the solder wettable surfaces to the limit of the solder volume without making a connection therebetween.
Generally, the surfaces to be connected by solder can be placed in sufficiently close proximity for connections to be made with very small volumes of solder materials. Such volumes of solder materials have been dispensed as a paste, containing particles of solder as a fine powder in a binder, by screening techniques, often using masks, as solder preforms such as the so-called C4 preform which may be appropriately placed and then caused to collapse in a controlled fashion upon application of heat. Production, use and rework of C4 solder deposits are discussed in detail on pages 366-391 of "Microelectronics Packaging Handbook" edited by R. R. Tummala et al., Van Nostrand Reinhold, N.Y., 1989.
More recently, solder materials have been deposited by evaporation or electroplating of solder materials. Electroplating is rapidly becoming a technique of choice for extremely close connection spacings possible at the present state of the art principally because lithographic techniques can assure that solder is placed at all desired locations while closely limiting the possibility that any solder materials at all will be placed at any other location.
As is known in the art, electroplating of solder materials requires the formation of common connections to all locations which are to be electroplated with solder materials with specific locations to which solder is to be electroplated exposed with a dielectric resist mask. The volume and height of the solder materials deposited is generally limited by the thickness of the resist used. Currently available resists can provide solder bump height of about 4 to 5 mils which is sufficient for most application. However, thicker resists are not readily available and, in any event, cause difficulty in lithographic exposure and patterning since the energy of exposures sufficient to expose a greater thickness of resist is also scattered within the resist, causing inaccuracy of the outline of the exposure pattern and the shape of the profile of the resist at apertures which adversely affects the accuracy of the solder volume deposited. Further, the masking and patterning may be compromised by inaccuracy of registration of the exposure for patterning the resist; causing inaccuracy of position of the deposited solder materials, particularly near the maximum resist thickness available.
Recently, some technologies have been developed which, while providing distinct and substantial advantages in circuit performance and package capacity (in terms of the number of circuits which may be included therein) as well as in chip integration density, present substantial new difficulties in formation of solder connections. In particular, circuit packages having connections made to edges of chips have become known in which solder bumps on a chip edge are pushed onto pins attached to the substrate. The so-called Single Inline Memory Module (SIMM) is exemplary of this type of package. However, in this and other types of edge connection packaging, due to difficulties of alignment and irregularities of chip edge geometry, particularly where several chips may be joined together prior to connection to a carrier, a maximum spacing of 4 -5 mils between a contact surface thereof and a connection surface of a substrate to which it is to be electrically and mechanically attached cannot be maintained. A solder bump height of 10 mils is considered to be required for formation of reliable solder connections having such geometries.
Nevertheless, the pitch of connections thereto must approach the pitch of connections to integrated circuits formed and or mounted in accordance with other technologies in order to exploit the potential integration density available in those technologies. Accordingly, forming solder deposits by electroplating has not been feasible since greater volumes of solder, higher dimensional extent above the carrier and higher geometrical accuracy of solder bumps is required to form connections than can be accommodated by thicknesses of currently available resists. At the same time, the pitch of connection pads closely approaches the limits at which solder connections can be reliably formed using preforms or by screening of solder materials and at which additional and unintended amounts of solder material can severely compromise manufacturing yield.
Accordingly, a need exists for accurate deposition of larger volumes of solder and with a greater dimensional extent above a surface than is available with currently available processes.